公司简介： 
 　
展讯通信有限公司(“展讯”)致力于无线通信及多媒体终端的核心芯片、专用软件和参 

考设计平台的开发， 
为终端制造商及产业链其它环节提供高集成度、高稳定性、功能强大的产品和多样化的 

产品方案选择。 

展讯成立于2001年4月，目前在美国的圣地亚哥和中国的上海、北京、深圳、天津、杭州
 
等地设有分公司和研发中心。 
 　
展讯自成立以来，始终坚持自主技术创新，以其长期积累的无线宽带技术、信号处理技 

术、IC设计技术、 
软件开发技术和经验，为无线通信终端制造商提供全方位的技术解决方案，包括新一代 

的专用基带芯片、 
多媒体芯片、射频芯片、协议软件和软件应用平台等。 展讯的产品支持多标准的宽带无
 
线通信， 
包括GSM、GPRS、EDGE、TD-SCDMA、W-CDMA、HSDPA、HSUPA以及未来的无线通讯标准。 

展讯以推动中国无线通信事业为己任，秉承以人才为根本、以世界为舞台的发展观，不 

断培养和激发员 
工创造力，结合全球的优势资源，为创造世界领先的技术和产品而不断前进！ 
 　
工作地点： 
 　
杭州滨江高新区盾安大厦 (滨江区区政府、江陵地铁站附近) 
 　
招聘职位(简历请投油箱：robert.chen@spreadtrum.com, 欢迎应届生投递相关招聘职位
 
）： 
 　
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SoC Validation Engineer 
Job Description: 
1.     　Responsible for SoC FPGA/PXP pre-silicon validation. 
2.     　Responsible for SoC post-silicon validation including function/ 
performance/power test and characteristics test. 
3.     　Support SoC mass production and chip driver development. 
 　
Requirement: 
1.     　Proficiency in C/Assembly Language and embedded software 　
development. 
2.     　Good with Mobile Application Processor driver development, chip 　
test or platform software development. 
3.     　Good to have knowledge of chip design 
4.     　Good with written and oral English 
5.     　Self-motivated and good team work. 
 　





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SoC Digital Design Engineer 
Job Description: 
1.     　Responsible for SOC/SUBSYS design/integration/verifications. 
2.     　Responsible for SOC design FPGA emulation/verification. 
3.     　Responsible for chip verification, performance analysis and 　
correlation. 
4.     　Responsible for SoC mass production. 
 　
Requirement: 
1.     　Proficiency in logic design, verification, synthesis, and testing. 
2.     　Proficiency in Verilog design, simulation, and debugging. 
3.     　Good with CPUs and relative bus design experiences. 
4.     　Good with multimedia, ISP, 2D/3D graphic, peripherals, etc. 　
knowledge. 
5.     　Good with UVM, OVM or VMM experiences. 
6.     　Good with written and oral English 
7.     　Self-motivated and good team work. 



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SoC Implementation Engineer 
Job Description: 
1.     　Responsible for synthesis and clean SDC generation based on RTL 　
released from Front-end team 
2.     　Responsible for DFT implementation, ATPG and pattern simulation 
3.     　Responsible for formal check and low power check 
4.     　Responsible for timing signoff with Layout team 
 　
Requirement: 
1.     　Proficiency in Synthesis ,DFT, Formal Check and STA 
2.     　Proficiency in related EDA tools, such as Synopsys/Cadence/Mentor 　
tools 
3.     　Proficiency in Verilog language 
4.     　Experience with logic design and simulation 
5.     　Experience with 65nm, 40nm or 28nm process is a plus 
6.     　Good knowledge of SOC design is a plus. 
7.     　Good with written and oral English 
8.     　Self-motivated and good team work 
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