Cadence SH 招聘 IC 前端设计、验证相关 实习职位

If you have interest, PLS send your CV to zhangyl@cadence.com

更多职位信息尽请关注Cadence中国招聘官方微信平台，微信号：Cadence中国招聘

实习时间：每周保证4天，维持半年以上
地点：浦东嘉里城(7号线，花木路站)
欢迎2016年毕业的微电子、集成电路、电子信息工程等相关专业的硕士生投递,表现优秀
者有机会转正。
实习安排：
通过严格的面试筛选后，能接触到EDA (电子设计自动化)行业最前沿的技术，并能得到
公司资深工程师的培训和指导，从中领略跨国美资企业的工作氛围与人文环境。

1.    Intern--Front-end Design Engineer (Location: SH)

   　Position Description: 
    DDR IP qualification and development/delivery flow optimization. The 
engineer should be able to act as a strong team member and contributor. 
Exercise judgment within generally defined practices and policies.
   　Specific duties include:
    Knowledge of IC design and verification flow
    Good script programming ( Tcl, perl, shell….)
 　
   　Position Requirements: 
    Essential Qualifications: Grade 2 MS student, with of applicable 
experience in electrical engineering, microelectronics, comparable 
engineering science or solid state physics. 
    Essential that the individual demonstrates strong communication, verbal 
and written.