Cadence招聘资深前端验证/设计工程师

Title: Lead/Senior Verification Engineer (数字前端验证)
Location： SH/BJ
更多职位信息敬请关注Cadence公众微信平台：Cadence中国招聘
If you have interest, PLS send your update CV to zhangyl@cadence.com

 　
Position Description: 
1.Deliver/implement advanced verification solutions by utilizing Cadence’s 
Incisive Verification product portfolio. The engineer should be able to act 
as a strong team member and contributor, leading team projects and 
initiatives. Exercise judgment within generally defined practices and 
policies.
Specific duties include:
1.Deep understanding on ASIC design and verification flow
2.Excellent knowledge of advanced verification methodology like eRM/OVM/UVM/
VMM
3.Familiar with Cadence’s Incisive Plan to Closure Methodology (IPCM)
4.Proficiency in System Verilog, System C and/or e (Specman)
5.Developing and using Verification Components (eVC,OVC,UVC,VIP)
6.Developing and using assertion based verification and formal analysis 
methods
7.Skilled in scripting language, such as Perl,C shell,Python,Makefile
8.Assessing the project verification requirements

Position Requirements: 
Essential Qualifications: 
1.BS degree with 4+ years of applicable experience, MS degree with 2+ years 
of applicable experience in electrical engineering, microelectronics, 
comparable engineering science or solid state physics. 　
2.Essential that the individual demonstrates strong communication, verbal 
and written. Requires good communication skills in English.

Desirable Qualifications: 
1.Will have demonstrated hands-on experience and expertise with Cadence 
verification design tools or equivalent tools, flows and methodologies 
required to execute a verification project.
2.Will have demonstrated successful completion of 3+ verification projects 
as an individual contributor
3.Will have DDR project verification experience



Title: Lead/Senior Design Engineer (数字前端设计)
Location: SH/BJ
更多职位信息敬请关注Cadence公众微信平台：Cadence中国招聘

If you have interest, PLS send your update CV to zhangyl@cadence.com
 
Position Description: 
Deliver/implement DDR/HBM IP. The engineer should be able to act as a strong 
team member and contributor. Exercise judgment within generally defined 
practices and policies.
     
Specific duties include:
1.Proficiency in logic design, simulation, synthesis, STA and testing
2.Proficiency in Verilog and its simulation environment
3.Good knowledge of IC design
4.At least two years’ experience driving complex IC development projects, 
excellent communication skills and the uncanny ability to both lead and 
contribute in a cooperative team environment.
 　
Position Requirements: 
1. Essential Qualifications: Must have BS degree with 4+ years of applicable 
experience, MS degree with 2+ years of applicable experience in electrical 
engineering, microelectronics, comparable engineering science or solid state 
physics. 
2. Essential that the individual demonstrates strong communication, verbal 
and written.
Requires good communication skills in English.

Desirable Qualifications: 
1.Will have demonstrated successful completion of 5+ design projects as an 
individual contributor
2.Familiar with JEDEC-DDR/HBM, DFI and AMBA protocols and have DDR project 
design experience


3. Title: Lead design engineer –STA
 　
Position Description: 
•In charge of IP and SOC logic design, and Implementation(focus on STA).
•Daily duties include: Digital IC micro-architecture, RTL coding, Logic 
Synthesis, Function Verification, DFT, and Static Timing Analysis.
•HDL language Knowledge, like verilog or vhdl is necessary.
•C/C++/perl/tcl/csh/python, UNIX, Linux experience are plus.
•Excellent analytical and problem-solving skills. Quick learner-able to 
learn and apply technical and complex topics.
•Excellent communication skills and the uncanny ability in a cooperative 
team environment are required.
•Self-motivated, result-oriented, can take ownership and follow-through on 
tasks.

Position Requirements: 
Essential Qualifications:
•Master degree or above  (2-5 year working experience)
•Major in Micro-electronics, Electronic Engineering, Computer Science, 
Information Technology or equivalent
•Ability to work effectively alone or as well as in the team.
•Essential that the individual demonstrates strong communication, verbal 
and written
•Requires good communication skills in English.

Desirable Qualifications:
•Good at any following skill sets: ASIC design, FPGA design, Computer 
architecture, SOC design based on ARM/MIPS.
•Experience of DDR